ordering number : enn7672a 92104tn (ot) / n1503tn (ot) no. 7672-1/8 sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircrafts control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. sanyo semiconductors data sheet LC72725M lc72725v lc72725nv cmos ic rds demodulation ic overview the lc72725 is an rds (radio data system) signal demodulation ic. this ic integrates a bandpass filter, the demodulation circuit, and buffer ram on a single chip and can read out rds data in slave mode operation with the provision of an external clock input. it also supports master mode, in which the data is read out in synchronization with an rds clock output provided by the ic itself. functions ? bandpass filter: switched capacitor filter (scf) ? rds demodulation: functions include 57khz carrier regeneration, clock regeneration, biphase decoding, and differential decoding ? buffer ram: stores 128 bits (about 100 ms) of data. ? data output: output can be switched between master mode and slave mode readout. ? rds id detection: supports id reset ? standby control: stops the crystal oscillator. ? low voltage: 2.7 to 5.5 v (lc72723: 4.5 to 5.5 v) ? improvement sample in crystal oscillation capability: lc72725nv ? fully adjustment free. ratings ? operating supply voltage: 2.7 to 5.5 v ? operating temperature: C20 to +70c ? packages: mfp16 and ssop16 (lc72723: dip 16 and mfp16)
no. 7672-2/8 LC72725M, lc72725v, lc72725nv parameter symbol conditions ratings unit maximum supply voltage v dd max vddd, vdda * C0.3 to +7.0 v v in 1 max test, mode, rst C0.3 to +7.0 v maximum input voltage v in 2 max xin, rdcl C0.3 to vddd + 0.3 v v in 3 max mpxin, cin C0.3 to vdda + 0.3 v vo1 max rds-id (ready) C0.3 to +7.0 v maximum output voltage vo2 max xout, rdda, rdcl C0.3 to vddd + 0.3 v vo3 max flout C0.3 to vdda + 0.3 v maximum output current io1 max xout, flout, rdda, rdcl +3.0 ma io2 max rdsCid (ready) +20.0 ma allowable power dissipation pd max (ta 85 c) mfp16 : 140 mw ssop16 : 100 mw operating temperature topr C20 to +70 c storage temperature tstg C40 to +125 c specifications absolute maximum ratings at ta = 25 c, vssd = vssa = 0 v. * : note that vdda must be less than or equal to vddd + 0.3 v parameter symbol conditions ratings unit min typ max supply voltage v dd vddd, vdda: vddd = vdda 2.7 5.5 v high-level input voltage v ih 1 test, mode, rst 0.7 vddd 6.5 v v ih 2 rdcl 0.7 vddd vddd v low-level input voltage v il test, mode, rst, rdcl 0 0.3 vddd v output voltage vo1 rdda, rdcl vddd v vo2 rdsCid (ready) 6.5 v input amplitude v in mpxin: f = 57 2 khz 1.6 50 mvrms vx in xin 400 1500 mvrms guaranteed oscillator operating range xtal xin, xout: c1 120 4.332 mhz crystal oscillator frequency deviation txtal xin, xout: fo = 4.332 mhz 100 ppm rdcl setup time t cs rdcl, rdda 0 s rdcl high-level time t ch rdcl 0.75 s rdcl low-level time t cl rdcl 0.75 s data output time t dc rdcl, rdda 0.75 s ready output time t rc rdcl, ready 0.75 s ready low-level time t rl ready 107 ms allowable operating ranges at ta = C20 to +70 c, vssd = vssa = 0 v, vddd = vdda.
no. 7672- 3 /8 LC72725M, lc72725v, lc72725nv parameter symbol conditions ratings unit min typ max input resistance rmpxin mpxin-vssa: f = 57 khz 100 k rcin cin-vssa: f = 57 khz 120 k internal feedback resistance rf xin 1.0 m center frequency fc flout 56.5 57.0 57.5 khz C3db bandwidth bwC3db flout 2.5 3.0 3.5 khz gain gain mpxin-flout: f = 57 khz 28 31 34 db att1 flout: ? f = 7 khz 30 db stop band attenuation att2 flout: f < 45 khz, f > 70 khz 40 db att3 flout: f < 20 khz 50 db reference voltage output vref vref: vdda = 3 v 1.5 v hysteresis v his test, mode, rst, rdcl 0.1 vddd v low-level output voltage v ol1 rdda, rdcl : i = 2 ma 0.4 v v ol2 rds-id (ready): i = 8 ma 0.4 v high-level output voltage v oh rdda, rdcl : i = 2 ma vddd C 0.4 v high-level input current i ih 1 test, mode, rst, rdcl : v i = 6.5 v 5.0 a i ih 2 xin: v i = vddd 2.0 11 a low-level input current i il 1 test, mode, rst, rdcl : v i = 0 v 5.0 a i il 2 xin: v i = 0 v 2.0 11 a output off leakage current i off rds-id (ready): v o = 6.5 v 5.0 a current drain idd vddd + vdda (vddd = vdda = 3 v) 5 ma electrical characteristics at ta = C20 to +70 c, vssd = vssa = 0 v, vddd = vdda. 1 8 16 9 10.0 0.63 6.4 0.15 0.35 1.27 (0.56) 4.4 (1.5) 1.7max 0.1 sanyo: mfp16 1 8 9 16 6.4 0.5 4.4 5.2 0.1 1.5max 0.65 0.22 (0.33) 0.15 (1.3) sanyo: ssop16 p ac ka g e dimensions unit: mm 3035b unit: mm 3178a [LC72725M] [lc72725v,lc72725nv]
pin assignment (mfp16/ssop16) no. 7672-4/8 LC72725M, lc72725v, lc72725nv block diagram LC72725M lc72725v lc72725nv top view
no. 7672-5/8 LC72725M, lc72725v, lc72725nv pin descriptions pin no. pin function i/o pin circuit type reference voltage output (vdda/2) output 3 vref base band (multiplex) signal input input 4 mpxin subcarrier output (filter output) output 7 flout subcarrier input (comparator input) input 8 cin analog system power supply (+3 v) 5 vdda analog system ground 6 vssa crystal element output (4.332 mhz) output 14 xout rds data output output 2 rdda rds clock output (master mode) rds clock input (slave mode) i/o 16 rdcl rds id/ready output (active high) output 1 rds-id/ready digital system power supply (+3 v) 12 vddd digital system ground 11 vssd test input 9 test crystal element input (or external reference signal input) input 13 xin readout mode setting (0: master, 1: slave) 10 mode rds id and ram reset (active high logic) 15 rst
rdcl/rdda output timing ? master mode no. 7672- 6 /8 LC72725M, lc72725v, lc72725nv rst operation ? master mode rdcl control in slave mode caution: after an rst input, the rdcl and rdda outputs stop at the high level until the first rds id detection. inputs and outputs note: the rds-id (ready) pin is an n-channel open-drain output, and data is read out by connecting a pull-up resistor. * lc72723: active-low test mode circuit operating mode rdcl pin rds-id/ready pin 0 0 master mode clock output rds-id output 0 1 slave mode clock input ready output 1 0 standby mode (crystal oscillator stopped) 1 1 ic test mode (cannot be set by users.) rst pin rst = 0 normal operation rst = 1 the rds-id and demodulation circuits are cleared, and (in slave mode) the ready state and memory are cleared. rds id/ready pin master mode rds-id output (active high) slave mode readout data ready output (active high)
no. 7672- 7 /8 LC72725M, lc72725v, lc72725nv rdcl (ic status) rdcl (microcontroller status) notes: 1. start rdcl clock input after the ready signal goes high. applications must stand by with rdcl held low when the ready pin is lo w. 2. each time the rdcl input is switched from low to high to low, the application must check the ready signal level after the perio d t rc has elapsed once rdcl has been set low. if ready is at the high level, the application may apply the next rdcl clock cycle. if ready is low , the application must stop rdcl input at that point. 3. when the above timing conditions are met, rdda can be read at either the rise or fall of the rdcl signal. 4. after the last data from memory has been read, ready will be low once the period t rc has elapsed after the fall of the rdcl signal. if even 1 bit of data has been written to memory, ready will be high and the application will be able to read that data. 5. when switching channels, it is desirable to immediately reset memory and the ready pin with an rst input. if this is not done, data received on the previous channel may remain in memory. when the ic is reset, data is not written until the rds-id is detected, and therefor e, the ready signal will go high after the rds-id is detected. (although the rds-id is not output in slave mode, it is detected internally i n the ic.) after an rst input, once an rds-id has been detected, all received data will be written to memory regardless of the rds-id detection state. 6. the readout mode may be switched between master and slave modes during readout. applications must observe the following points to assure data continuity during this operation. ? data acquisition timing in master mode data must be read on the falling edge of rdcl. ? timing of the switch from master mode to slave mode after the rdcl output goes low and the rdda data has been acquired, the application must set mode high immediately. then, the microcontroller starts output by setting the rdcl signal low. the microcontroller rdcl output must start within 840 s (tms) after rdcl went low. in this case, if the last data read in master mode was data item n, then data starting with item n+1 will be written to memory. ? timing of the switch from slave mode to master mode after all data has been read from memory and ready has gone low, the application must then wait until ready goes high once agai n the next time (timing a in the figure), immediately read out one bit of data and input the rdcl clock. then, at the point ready goes low , the microcontroller must terminate rdcl output and then set mode low. the application must switch mode to low within 840 s (tms) after ready goes high (timing a in the figure). parameter symbol conditions ratings unit min typ max rdcl setup time t cs rdcl, rdda 0 s rdcl high-level time t ch rdcl 0.75 s rdcl low-level time t cl rdcl 0.75 s data output time t dc rdcl, rdda 0.75 s ready output time t rc rdcl, ready 0.75 s ready high-level time t rh ready 107 ms
ps no. 7672- 8 /8 LC72725M, lc72725v, lc72725nv this catalog provides information as of september, 2004. specifications and information herein are subject to change without notice. lc72725 sample application connection circuit (for master mode operation) caution: if the rst pin is unused, it must be connected to ground. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customers products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customers products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the delivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. xout vssd 2 1 15 16 14 rds-id rdda rdcl 13 10 9 xin mode rst rdda rdcl rdsid/ready cin flout vssa vdda mpxin vref 4.332 mhz 22 pf vssa vdda 8 7 6 5 4 + 3 10 f vssa mpxin 560 pf 0.1 f 330 pf 3 v 2 k 12 11 vssd vssd vddd 0.1 f vddd rs t test 22 pf
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